The invention relates to a method of fabricating a semiconductor device having a polycrystalline silicon resistive layer, and more particularly to a method of fabricating a polycrystalline silicon resistive layer having a reduced resistivity, which is involved in high frequency bipolar transistor integrated circuits.
High frequency semiconductor devices such as high frequency bipolar transistor integrated circuits includes a resistance of polycrystalline silicon, which are widely used in the prior art. The reason of those are as follows. It is, generally, desirable for such high frequency semiconductor device to reduce the parasitic capacitance. Actually, the employment of the polycrystalline silicon resistive layer in such high frequency bipolar transistor integrated circuits permits the parasitic capacitance to substantially be reduced as compared with the employment of a diffused resistor. The polycrystalline silicon resistive layer is also doped with a dopant in order to reduce the resistivity. Thus, such semiconductor devices including the doped polycrystalline silicon resistive layer are likely to suitable as high frequency devices.
In the prior art, the method of fabricating a high frequency bipolar transistor integrated circuits including the doped polycrystalline silicon resistive layer may be fabricated by following steps which are illustrated in FIGS. 1A to 1F.
With reference to FIG. 1A, a p.sup.- -type silicon substrate 2 is prepared to form the high frequency bipolar transistor integrated circuits. An n.sup.+ -type silicon buried layer 3 is formed on the p.sup.- -type silicon substrate 2, after which an n-type epitaxial layer 1 is deposited on the n.sup.+ -type silicon buried layer 3. Further, p.sup.+ -type isolation diffused layers 4 are formed in the p.sup.- -type silicon substrate 2.
Subsequently, a thick silicon oxide layer 5 is formed to implement an isolation of an active region from others. An n.sup.+ -type collector layer 6 is formed in the n-type epitaxial layer 1. A silicon oxide film layer 8 is deposited so as to cover the active region, or the n-type epitaxial layer 1 including the n.sup.+ -type collector layer 6. A p-type base layer 7 is formed in the n-type epitaxial layer 1 so as to be separated from the n.sup.+ -type collector layer 6. After that, a silicon nitride film layer 9 is deposited so as to cover the entire surface of the device, and thus the silicon oxide film layer 8 as well as the silicon oxide thick layer 5.
With reference to FIG. 1B, the silicon nitride film 9 is formed with openings which will serve as contact holes, and thus a base contact hole, an emitter contact hole and a collector contact hole respectively. The collector contact hole exists directly over the n.sup.+ -type collector layer 6. A base contact layer 18 is formed in the base layer directly under the base contact hole.
With reference to FIG. 1C, a polycrystalline silicon layer 11 is deposited on the silicon nitride film layer 9 by using a deposition method such as a chemical vapor deposition. Concurrently, the polycrystalline silicon layer 11 is also deposited in the openings, or the base, emitter and collector contact holes respectively by which the polycrystalline silicon layer 11 is made into contact with the base contact layer 18 through the base contact hole, and made into contact with a part of the base layer, at which an emitter region will be formed, through the emitter contact hole, in addition made into contact with the n.sup.+ -type collector layer 6 through the collector contact hole. Such polycrystalline silicon layer 11 is subjected to an introduction of an n-type dopant such as arsenic or phosphorus by using an ion-implantation.
With reference to FIG. 1D, a silicon oxide film layer 20 is deposited to cover the polycrystalline silicon layer 11. A heat treatment at a temperature of 950.degree. C. is so accomplished that a thermal diffusion permits making the n-type dopant such as arsenic or phosphorus be driven from the polycrystalline silicon layer 11 into the p-type base layer 7 in the emitter contact hole, in addition into the n.sup.+ -type collector layer 6. As a result of the thermal diffusion, an emitter region 15A is formed in the p-type base layer 7 directly under the emitter contact hole. Concurrently, a collector region 16A is formed in the n.sup.+ -type collector layer 6.
With reference to FIG. 1E, a photo resist is previously subjected to patterning by using photo etching so as to have a predetermined pattern. Subsequently, the polycrystalline silicon layer 11 is subjected to photo etching with using the photo resist pattern as a mask so that the polycrystalline silicon layer 11 remains in the vicinity of the emitter and collector contact holes, in addition on a predetermined area over the silicon oxide thick layer 5, and thus an area opposite to the active region including the base layer 7, emitter and collector regions 15A and 16A. As a result of those photo etching process, an emitter polycrystalline silicon contact 15B is formed on the emitter region 15A and a collector polycrystalline silicon contact 16A is formed on the collector region 16B. Concurrently, a polycrystalline silicon resistive layer 12 is formed on the predetermined area over the silicon oxide thick layer 5 through the silicon nitride film layer 9. The polycrystalline silicon resistive layer 12 has a predetermined dimensions, or the thickness, the width and the length so as to serve as a resistance element in which the thickness is defined by, and thus is the same as the thickness of the polycrystalline silicon layer 11.
With reference to FIG. 1F, a silicon oxide film 14 is so deposited as to cover the polycrystalline silicon resistive layer 12, after which contact holes 19 are formed in the silicon oxide film 14, which is followed by providing electrodes (not illustrated) in the contacts holes. Through the above processes, the fabrication of the high frequency bipolar transistor circuit device involving the polycrystalline silicon resistive layer is completed.
Subsequently, the fabrication process of the polycrystalline silicon resistive layer 12 will again be described in conciseness to clear the matters to be solved by the subject of the present invention directing to the method of fabricating the polycrystalline silicon resistive layer involved in the high frequency semiconductor device such as the high frequency bipolar transistor integrated circuit device.
With reference to FIG. 2A, a silicon oxide thick layer 5 is formed on a p.sup.- -type silicon substrate 2. A polycrystalline silicon layer 11 is deposited on the the silicon oxide thick layer 5. Subsequently, the ion-implantation of an n-type dopant such as arsenic or phosphorus is so accomplished that the n-type dopant is doped into the entire surface of the polycrystalline silicon layer 11. After forming a silicon oxide film layer 20 covering the polycrystalline silicon resistive layer 11, a heat treatment such as annealing of the polycrystalline silicon layer 11 is required to implement an activation of the dopant.
With reference to FIG. 2B, the polycrystalline silicon layer 11 is subjected to photo etching by using the photo resist pattern which is not illustrated. The improvement of the definition of the patterned polycrystalline silicon resistive layer 12 serving as a resistance also requires the above heat treatment such as annealing.
With reference to FIG. 2C, the silicon oxide film 14 is so formed as to cover the polycrystalline silicon resistive layer 12. The silicon oxide film 14 are formed with the contact holes 19 in which contacts 20 are provided.
Such high frequency bipolar transistor integrated circuit device involving the resistance element comprising the polycrystalline silicon resistive layer 12 has been engaged with following considerable disadvantages. In view of circuit designs, the set forth polycrystalline silicon resistive layer 12 is required to have a low resistivity, typically a sheet resistance of 100 to 200 ohms/square. The sheet resistance depends upon the heat treatment for the polycrystalline silicon resistive layer 12. For instance, a heat treatment at a high temperature of 950.degree. C. implements the dopant activation which permits providing a desirable lower sheet resistance to the polycrystalline silicon resistive layer 12. Then, the implementation of the dopant activation at a high temperature provides a reduction of the sheet resistance.
Nevertheless, the implementation of a high temperature heat treatment for a relatively long time, concurrently, serves as a prevention against the realization of the high frequency bipolar transistor. Such implementation of a high temperature heat treatment causes a thermal diffusion of the base layer 7, which makes the thickness be increased. Such diffused thick base layer is no longer able to provide a desirable high frequency characteristic to the bipolar transistor. For example, the realization of a cut-off frequency f.sub.T of 10 GHz limits a temperature of the heat treatment to 950.degree. C. But, the realization of a cut-off frequency f.sub.T of 20 GHz limits a temperature of the heat treatment down to 900.degree. C.
On the other hand, from the definition of the sheet resistance, it is no doubt appeared that the sheet resistance is inversely proportional to the thickness of the polycrystalline silicon resistive layer 12. Thus, the enlargement of the thickness of the polycrystalline silicon resistive layer 12 permits the sheet resistance to be reduced. FIG. 3 illustrates a variation of the sheet resistance values possessed by the polycrystalline silicon resistive layer 12 versus the dose of an ion-implantation for the thicknesses of 1500 angstroms and of 3000 angstroms in case that a heat treatment is accomplished at a temperature of 900.degree. C. for 40 minutes. When the thickness is 1500 angstroms, the sheet resistance is 350 ohms/square. From the FIG. 3, it is understood that the thickness of 3000 angstroms provides a lower sheet resistance as compared with the thickness of 1500 angstroms.
From the above descriptions, it is required for such high frequency bipolar transistor integrated circuit device to accomplish a relatively low temperature heat treatment so as to prevent a very thin base layer to be enlarged by a thermal diffusion. It is further required to increase the thickness so as to reduce the sheet resistance of the polycrystalline silicon resistive layer 12, typically up to 3000 angstroms.
Nevertheless, the thickness of the polycrystalline silicon resistive layer 12 is defined by the thickness of the polycrystalline silicon layer 11 which has been deposited, and thus is the same as thicknesses of the polycrystalline silicon emitter contact 15B and the polycrystalline silicon collector contact 16B. As the thickness of the polycrystalline silicon resistive layer 12 is increased up to 3000 angstroms, the thicknesses of the polycrystalline silicon emitter contact 15B and of the polycrystalline silicon collector contact 16A are also forced to be increased up to 3000 angstroms. The minimization of the bipolar transistor integrated circuits renders formations of the emitter and collector contacts 15B and 16B difficult due to the large thickness of the above contacts 15A and 16A. This is also likely to cause an electrical short between the emitter and collector contacts 15A and 16A, by which the yield of the device are also lowered.
To combat those problems, it may be proposed that the polycrystalline silicon resistive layer 12 is formed prior to the formation of the emitter region 15A so as to prevent the resistive layer 12 and the emitter and collector contacts 15B and 16B to respectively be formed from the common polycrystalline silicon layer 11. This allows the polycrystalline silicon resistive layer 12 to have a larger thickness than that of the emitter and collector contacts 15B and 16B. However, in this case, the realization of a desirable and precise pattern by etching of the polycrystalline silicon resistive layer 12 requires an implementation of a heat treatment at a temperature of 900.degree. C. for 15 minutes or more. Such implementation of the heat treatment at a high temperature for a relatively long time causes the very thin base layer 7 to be re-diffused, and thus the thickness to be increased. As a result of the re-diffusion of the base laye 7, such bipolar transistor involving the base layer 7 having an enlarged thickness which has been subjected to such undesirable heat treatment is no longer able to possess a high frequency characteristic as illustrated in FIG. 4.
Furthermore, the above heat treatment at a high temperature for a relatively long time for the accomplishment of the activation of the dopant in the polycrystalline silicon resistive layer 12 also causes the very thin base layer 7 to be re-diffused, and thus enlarged.
In addition, in view of device designs, the polycrystalline silicon resistive layer 12 is required to have a precise resistance value equal to a predetermined value. The resistance value of the polycrystalline silicon resistive layer 12 depends upon the dimensions, or the thickness, the length and the width. In view of circumstances, it is difficult for the present etching technology to prevent dimensional errors of the width and the length. Such dimensional error caused by the etching process makes bounds fencing the doped area in the polycrystalline silicon resistive layer 12 variable, since the dopant exists at an edge portion defined by etching of the polycrystalline resistive layer 12. The etching process is accomplished after the doping process. The relatively large dimensional error of the polycrystalline silicon resistive layer 12 provides a substantial large variation of the resistance value. In view of the device designs, such variation of the resistance value caused by the dimensional error is no doubt undesirable.
It is, therefore, considerable to develop a novel method of fabricating the polycrystalline silicon resistive layer having a reduced resistivity, and thus a lower sheet resistance which is suitable as a resistive element involved in the high frequency bipolar transistor integrated circuit device. It is further desirable that such novel fabrication method of the polycrystalline silicon resistive layer permits preventing the thickness of the base layer to be enlarged by the thermal diffusion which is caused by such heat treatment for accomplishment of the activation of the dopant so as to reduce the sheet resistance or for improvement of the definition, or pattern of the polycrystalline silicon resistive layer. It is also required to develop a novel fabrication method of the polycrystalline silicon resistive layer having a larger thickness than that of the emitter and collector contacts. It is additionally required to develop a novel fabrication method of the polycrystalline silicon resistive layer, which permits preventing a variation of the resistance values which is caused by the dimensional error of the width and the length generated in the photo etching process, because such variation of the resistance values is causative of affections toward circuit performances.